The present invention relates to a method of and a system for controlling the brightness of a plasma display panel (hereinafter referred to as PDP), particularly for controlling the brightness of a picture reproduced from video signals and displayed on the PDP.
FIG. 10 is an explanatory view indicating a conventional driving system for driving an AC discharge type PDP whose luminescent units are arranged in a matrix manner.
As shown in FIG. 10, the conventional driving system has a signal processing section 1 for processing inputted composite video signals and for producing DVD driving signals, a display section 2 for receiving the DVD driving signals fed from the signal processing section 1 and for displaying reproduced picture on the PDP.
In the signal processing section 1, composite video signals inputted from the outside are processed in an A/D converter 3, so that said video signals will become in synchronism with a timing pulse produced from a timing pulse generating circuit 7, and are converted into 8-bit digital picture element data signals which are then fed to a frame memory 4.
The frame memory 4, in accordance with a taking-in signal and a reading-out signal both of which are all fed from a memory control circuit 8, is adapted to successively take-in picture element data from the digital picture element data signal fed from the A/D converter 3, and to read-out the taken-in picture element data which is then fed to an output signal processing circuit 5.
The output signal processing circuit 5 is provided to process the digital picture element data signal so as to produce for each field a picture element data signal having a mode (8 bit) corresponding to a brightness gradation of the filed. Then, the picture element data signal is synchronized with a timing signal fed from a timing signal generating circuit 9 and is further fed to a picture element data pulse generating circuit 10.
In the signal processing section 1, composite video signals inputted from the outside are also fed to a synchronizing signal separation circuit 6 which is provided to extract a horizontal synchronizing signal and a vertical synchronizing signal from the composite video signals. The extracted horizontal synchronizing signal and vertical synchronizing signal are then supplied to a timing pulse generating circuit 7.
The timing pulse generating circuit 7 is provided to produce various timing pulses in accordance with the above horizontal and vertical synchronizing signals. The various timing pulses are fed to the A/D converter 3, a memory control circuit 8 and a reading-out timing signal generating circuit 9.
Here, the A/D converter 3 is provided to, in synchronism with the timing pulse fed from the timing pulse generating circuit 7, perform analog/digital conversion for the composite video signals fed from the outside to the signal processing section 1.
The memory control circuit 8 is provided to produce a taking-in signal (in synchronism with a timing pulse fed from the timing pulse generating circuit 7) and a reading-out signal (in synchronism with a reading-out timing signal fed from the reading-out timing signal generating circuit 9) to the frame memory 4. Accordingly, the frame memory 4 can take-in picture element data from digital picture element data signal fed from the A/D converter 3, and can read-out the taken-in picture element data.
The reading-out timing signal generating circuit 9 receives a timing pulse fed from the timing pulse generating circuit 7, and produces a reading-out timing signal in accordance with said timing pulse. The reading-out timing signal is fed to the memory control circuit 8, the output signal processing circuit 5, further to a row electrode driving pulse generating circuit 11 of the display section 2.
In this way, the memory control circuit 8 can produce a reading-out signal to the frame memory 4, and the output signal processing circuit 5 can produce picture element data to a picture element data pulse generating circuit 10 of the display section 2.
Referring to FIG. 11, the display section 2 comprises a PDP 12 which includes a plurality of row electrodes Xi, Yi (i=1, 2 . . . n) arranged in parallel with one another on an inner surface of a front glass substrate 12A serving as a picture display panel.
Further, a dielectric layer 12B is provided to cover the row electrodes Xi, Yi (i=1, 2 . . . n). A magnesium oxide (MgO) layer 12C is formed on the dielectric layer 12B, an electric discharge space 12E is formed between the magnesium oxide layer 12C and a rear glass substrate 12D.
A plurality of column electrodes Dj (j=1, 2 . . . m) are arranged in parallel with one another on an inner surface of the rear glass substrate 12D, in a manner such that the column electrodes Dj (j=1, 2 . . . m) are perpendicular to the row electrodes Xi, Yi (i=1, 2 . . . n).
In practice, each pair of row electrodes Xi, Yi are used to form one displaying line within the PDP, each intersection formed by one pair of row electrodes Xi, Yi with one column electrode Dj forms a picture element cell.
The picture element data pulse generating circuit 11 of the display section 2 is connected with the plurality of column electrodes Dj (j=1, 2 . . . m) for producing picture element data pulses DPj(j=1, 2 . . . m) corresponding to the picture element data fed from the output signal processing circuit 5 of the signal processing section 1, said picture element data pulses DPj (j=1, 2 . . . m) being applied to the column electrodes Dj (i=1, 2 . . . m).
The row electrode driving pulse generating circuit 11 is connected with the plurality of row electrodes Xi, Yi (i=1, 2 . . . n), so as to produce the following pulses to these row electrodes Xi, Yi (i=1, 2 . . . n) in accordance with the reading-out timing signals fed from the reading-out timing signal generating circuit 9 of the signal processing section 1. In fact, the pulses produced by the row electrode driving pulse generating circuit 11 and fed to the plurality of row electrodes Xi, Yi (i=1, 2 . . . n), are reset pulses RPx, RPy for effecting an electric discharge between each pair of row electrodes Xi, Yi (i=1, 2 . . . n) to generate charged particles in the discharge space 12E, priming pulses PP for reforming the charged particles, scanning pulses SP for writing-in picture element data, sustaining pulses LPx, LPy for maintaining discharge luminescence, erasing pulses EP for erasing wall electric charges.
FIG. 12 is a timing chart indicating various timings of the above pulses to be applied to the row electrodes Xi, Yi (i=1, 2 . . . n).
As shown in FIG. 12, a reset pulse RPx of a positive voltage is applied to each of the row electrodes Xi (i=1, 2 . . . n), while another reset pulse RPy of a negative voltage is applied to each of the row electrodes Yi (i=1, 2 . . . n). With the application of the reset pulses RPx and RPy, an electric discharge is induced in a space between each pair of row electrodes Xi, Yi (i=1, 2 . . . n), whereby generating charged particles within the electric discharge space 12E corresponding to all the picture element cells.
By virtue of the charged particles, upon completion of the electric discharge, a predetermined amount of wall charges will form in the same manner in all the picture element cells within the dielectric layer 12B.
Here, a time period until the formation of the wall charges is called an all-at-once reset period.
On the other hand, the picture element data pulse generating circuit 10 operates to successively apply picture element data pulses DPj (j=1, 2 . . . m) (each having a voltage corresponding to picture element data) to the column electrodes Dj (j=1, 2 . . . m).
As shown in FIG. 12, just before the picture element data pulse generating circuit 10 applies picture element data pulse DPj (j=1, 2 . . . m) to the column electrodes Dj (j=1, 2 . . . m), the row electrode driving pulse generating circuit 11 applies a priming pulse PP of a positive polarity to each of the row electrodes Yi (i=1, 2 . . . n). Then, a scanning pulse SP having a predetermined small pulse period and a negative polarity is successively applied to each of the row electrodes Yi (i=1, 2 . . . n), in synchronism with a timing of the picture element data pulse DPj (j=1, 2 . . . m).
With the application of the priming pulse PP, the charged particles formed in the all-at-once reset period but have decreased with the passing of time, can be increased again. Further, when the scanning pulses SP are applied during a period the charged particles are still existing, an electric potential difference between a scanning pulse SP and a picture element data pulse DPj will occur, causing a selected discharge therebetween, thereby effecting a predetermined writing-in of the picture element data.
Namely, a scanning pulse SP can serve as a trigger for selectively erasing (corresponding to picture element data) wall charges formed due to charged particles in each picture element cell within the dielectric layer 12B, thereby effecting a predetermined writing-in of the picture element data, depending upon whether or not electric discharges are caused between the row electrodes Yi (i=1, 2 . . . n) and the column electrodes Dj (j=1, 2 . . . m) and wall electrodes are thus erased.
For example, the voltage of each of the picture element data pulses DPj (j=1, 2 . . . m) applied to a picture element cells will be V (having a positive polarity) if a picture element data indicates a logic xe2x80x9c1xe2x80x9d, but will be 0 if a picture element data shows a logic xe2x80x9c0xe2x80x9d. On a line within the PDP 12 to which a scanning pulse SP is applied, when a picture element data indicates a logic xe2x80x9c1xe2x80x9d, an electric potential difference between a scanning pulse SP and a picture element data pulse DPj (i=1, 2 . . . m) becomes large, thus there will be a minor electric discharge (corresponding to the period of a scanning pulse SP) between a row electrode Yi and a column electrode Dj, thereby erasing wall charges in the dielectric layer 12B corresponding to picture element cells. At this moment, since a time for the electric discharge is short, there would be no wall charges newly formed in the dielectric layer 12B.
On the other hand, when the picture element data (corresponding to picture element cell) indicates a logic xe2x80x9c0xe2x80x9d, an electric potential difference between a scanning pulse SP and a picture element data pulse DPj (i=1, 2 . . m) is small. As a result, there will not be any electric discharge between a row electrode Yi and a column electrode Dj, rendering wall charges to remain within the dielectric layer 12B corresponding to picture element cells.
Here, a period necessary for writing-in the picture element data by virtue of the erasing of the wall charges is called an address period.
Next, the row electrode driving pulse generating circuit 11 operates to continuously apply a sustaining pulse LPx of positive polarity to each row electrode Xi, and continuously apply a sustaining pulse LPy of positive polarity to each row electrode Yi in a timing slightly later than a timing for applying the pulse LPx.
With the application of the sustaining pulses LPx and LPy, discharge luminescence occurs only in picture element cells where wall charges are remaining within the dielectric layer 12B. Such discharge luminescence may be maintained during a period when the sustaining pulses LPx and LPy are being applied continuously.
By virtue of such discharge luminescence, a picture will then be displayed on the PDP 12.
Here, a period during which the discharge luminescence is maintained by continuously applying sustaining pulses LPx and LPy is called a discharge maintaining period.
After the discharge luminescence has been maintained for a predetermined period, the row electrode driving pulse generating circuit 11 operates to apply an erasing pulse EP having a negative polarity to each row electrode Yi, so as to erase the wall charges remaining in the dielectric layer 12B, thereby finishing the display of one field of picture.
However, with an AC discharge type matrix display PDP, since there is a significant temperature difference between portions of discharge luminescence and the portions of non-discharge luminescence, a problem such as cracking might occur on the PDP.
In order to prevent a possible cracking on a PDP, there has been suggested an Automatic Brightness/Beam Limiter for limiting a picture brightness when displaying a stationary picture on a display panel, as disclosed in the applicant""s earlier application (Japanese Patent Application No. 9-187827).
FIG. 13 is a block diagram indicating a brightness limiting system disclosed by the applicant in the above-mentioned earlier application. With such a brightness limiting system, a composite video signal is decomposed into various analogue color signals R, G, B (Red, Green, Blue) by virtue of a color signal generating circuit (not shown).
As shown in FIG. 13, the color signals R, G, B are applied to A/D converters 20R, 20G, 20B to be converted into digital signals which are further fed to multipliers 21R, 21G, 21B in which each digital signal is multiplied by a multiplication coefficient, thereby setting brightness levels of various color signals R, G, B.
The various color signals R, G, B, whose brightness levels have been set, are fed to a frame memory (not shown) and further to an output signal processing circuit (not shown) so as to be applied to a display section (not shown), in the same manner as shown in FIG. 10.
However, the multiplication coefficients for use in setting the brightness levels of various color signals R, G, B may be determined in the following way.
Namely, color signals R, G, B, which have been converted into digital signals in A/D converters 20R, 20G and 20B, are fed to a synthesizing circuit 22 so as to be synthesized with a brightness signal. The systhesized signal is then fed to an APL (Average Picture Level) calculating circuit 23.
The APL calculating circuit 23 is provided to divide video signal of one field picture into eight blocks in vertical direction (see FIG. 14) and to calculate an APL value for each block. The APL values are then fed to an APL adder circuit 24.
The APL adder circuit 24 is provided to adder together the APL values of two adjacent blocks to obtain an added APL value to be fed to a comparator circuit 25.
The comparator circuit 25 is provided to compare an added APL value with a reference value set in advance in a reference value generating circuit 26, with a comparing result fed to a multiplication coefficient setting circuit 27.
The multiplication coefficient setting circuit 27 operates to set multiplication coefficients for multipliers 21R, 21G, 21B, in accordance with comparison results fed from the comparator circuit 25. Namely, if an added APL value is larger than a reference value, a multiplication coefficient (preset in the circuit 27 and smaller than 1), will be fed to each of the multipliers 21R, 21G, 21B. The multipliers 21R, 21G, 21B will thus operate to multiply the color signals R, B, G with the multiplication coefficient, so as to reduce the brightness level of color signals R, B, G.
On the other hand, if each of added APL values is smaller than a reference value, a multiplication coefficient (preset in the circuit 27 and equal to 1), will be fed to each of the multipliers 21R, 21G, 21B, so as not to reduce the brightness level of color signals R, B, G.
For instance, if a reference value preset in the circuit 26 is 400, in a pattern of FIG. 14A (in which numerical numbers are used to represent APL values of the blocks), since each of added APL values of two adjacent blocks is smaller than 400, only a multiplication coefficient equal to 1 is outputted from the multiplication coefficient generating circuit 27, so as not to reduce the brightness level of color signals R, B, G.
On the other hand, as shown in a pattern of FIG. 14B, if an added APL value of two adjacent blocks (block 4 and block 5) is larger than the preset reference value 400, multiplication coefficient preset in the circuit 27 and smaller than 1 (for example 0.5), will be fed to the multipliers 21R, 21G, 21B. The multipliers 21R, 21G, 21B will operate to multiply the color signals R, B, G with the multiplication coefficient (0.5), so as to reduce the brightness level of various color signals, as shown in FIG. 14C (APL value of each block has been reduced to xc2xd of its original value).
With the use of the above brightness control system, it is possible to reduce the picture brightness on some areas of a PDP where bright picture portions are collected, thereby preventing occurence of cracking on the PDP.
However, it has been proved that the above conventional brightness control system (Automatic Brightness/Beam Limiter) is effective only in a case where a bright portion xcex1 of a stationary picture is collecte in a leteral direction (see FIG. 15), but is not effective in a case where a bright portion a of a stationary picture is collected in a vertical direction (see FIG. 16). The reason responsible for the case of FIG. 16 is that APL values of all the blocks are low, an added APL value of every two adjacent blocks is lower than a predetermined reference value, hence disabling the brightness control system (Automatic Brightness/Beam Limiter), and making it impossible to prevent a cracking in a PDP.
It is an object of the present invention to provide an improved method of controlling the brightness of a PDP (plasma display panel), capable of preventing a cracking on the PDP, regardless of what pattern of a stationary picture is displayed on the PDP, thereby solving the above-mentioned problems peculiar to the above-discussed prior arts.
According to the present invention, there is provided a method of controlling a brightness of a picture displayed on a plasma display panel by increasing or decreasing said brightness, said method comprising: determining whether a video signal to be fed to the plasma display panel is a signal indicating a stationary picture; reducing the brightness of a picture displayed on the plasma display panel if it is determined that a video signal to be fed to the plasma display panel is a signal indicating a stationary picture.
In one aspect of the present invention, one average brightness level of a video signal to be fed to the plasma display panel is detected during a predetermined period, said one average brightness level is then compared with a former average brightness level detected immediately before the detection of said one average brightness level, so as to obtain a difference between said one average brightness level and said former average brightness level.
In another aspect of the present invention, when the difference between said one average brightness level and said former average brightness level is smaller than a predetermined value and such condition has continued for a predetermined time, it is determined that said video signal is a signal indicating a stationary picture.
In a further aspect of the present invention, when it is determined that a video signal to be fed to the plasma display panel is a signal indicating a stationary picture, the number of sustaining pulses for maintaining luminescent discharge on the plasma display panel is reduced.
In a still further aspect of the present invention, the number of sustaining pulses for maintaining luminescent discharge on the plasma display panel is reduced gradually step by step.
In one more aspect of the present invention, when it is determined that a video signal to be fed to the plasma display panel is a signal indicating a stationary picture, multiplication coefficients are made smaller which will be multiplied with video signals to be fed to the plasma display panel to adjust the brightness of the stationary picture displayed on the plasma display panel.
Further, according to the present invention, there is provided a system for controlling a brightness of a picture displayed on a plasma display panel by increasing or decreasing said brightness, said system comprising: determining means for determining whether a video signal to be fed to the plasma display panel is a signal indicating a stationary picture; brightness reducing means for reducing the brightness of a picture displayed on the plasma display panel if it is determined that a video signal to be fed to the plasma display panel is a signal indicating a stationary picture.
In one more aspect of the present invention, the above determining means comprises: average brightness level detecting means for detecting during a predetermined period one average brightness level of a video signal to be fed to the plasma display panel; calculating means for comparing said one average brightness level with a former average brightness level detected immediately before the detection of said one average brightness level and for obtaining a difference between said one average brightness level and said former average brightness level; monitor means for monitorring whether the difference obtained by the calculating means has continuously been smaller than a predetermined value for a predetermined time. In particular, when the monitor means determines that the difference obtained by the calculating means has continuously been smaller than a predetermined value for a predetermined time, it is determined that said video signal is a signal indicating a stationary picture.
In still one more aspect of the present invention, the brightness reducing means is means capable of reducing the number of sustaining pulses for maintaining luminescent discharge on the plasma display panel.
In still one more aspect of the present invention, the brightness reducing means is capable of reducing the number of the sustaining pulses gradually step by step.
In still one more aspect of the present invention, the brightness reducing means is means capable of reducing multiplication coefficients to be multiplied by video signals to be fed to the plasma display panel so as to adjust the brightness level of the video signals.
The above objects and features of the present invention will become better understood from the following description with reference to the accompanying drawings.